PALO ALTO, 26 AUG 2026 — Nvidia used Hot Chips 2026 to open up the architecture of Vera, the CPU that will pair with its Rubin GPUs. The package holds six dies on one interposer and 88 custom Olympus cores.
Much of the coverage has compressed those two numbers into a single claim, that the 88 cores are split across six chiplets. They are not. All 88 sit on one monolithic compute die, and the other five dies handle memory and I/O. That distinction is the point of the design.
What the package actually holds
Vera is a disaggregated package with a deliberately undisaggregated centre.
One die carries the full complement of cores. Around it, the memory path and the I/O path have been moved onto separate chiplets, the latter carrying 96 PCIe and CXL lanes for accelerators and network cards. Memory is eight 128-bit LPDDR5X channels, chosen for energy efficiency rather than peak bandwidth. NVLink-C2C provides the coherent link to a Rubin GPU, or to a second Vera in a two-socket configuration.
So the package is chipleted and the processor is not. Both statements are true, and collapsing them loses the point.
Why the compute die stayed whole
The industry has spent most of a decade moving the other way. AMD built its server business on chiplets for compelling economic reasons. Smaller dies yield and bin better, and can be mixed across product lines instead of being fabricated as one large and fragile object.
The cost is latency between them. When cores are divided across compute dies, cache lines that live on the other die take longer to reach, and a thread whose working set straddles the boundary pays for the crossing. On chiplet designs this shows up as a well-documented penalty and a great deal of software effort spent keeping related work on the same die.
Nvidia's second-generation Scalable Coherency Fabric distributes last-level cache in a mesh across the single compute die, so there is no cross-die hop to pay for at all. That choice buys latency consistency and pays for it in manufacturing difficulty, which is the trade every chiplet design makes in the opposite direction.
The reason it is worth the price is the workload. Nvidia is explicit that Vera targets control-heavy, latency-sensitive work — agent orchestration and reinforcement learning, where the CPU spends its time deciding what the GPUs do next. That is a serial, branchy, latency-bound job, and it is close to the worst case for a design where a cache miss might cross a package boundary.
Spatial multithreading is not the SMT you know
The most interesting detail got the least attention. Vera's multithreading statically partitions core resources between threads rather than sharing them dynamically.
Conventional simultaneous multithreading lets two threads compete for the same execution resources, which raises total throughput and makes any individual thread's timing depend on what its neighbour happens to be doing. That variability is tolerable in a throughput server and corrosive in a latency-sensitive one, and it is why some operators disable SMT outright.
Static partitioning gives up some peak throughput and returns predictability. A thread gets its allocation regardless of the neighbour's behaviour. For an orchestration role where tail latency matters more than average throughput, that trade-off makes sense, and it is consistent with the rest of the design.
Low-power memory on a flagship part
Choosing LPDDR5X for a datacentre CPU looks like a downgrade until you ask what this processor is for.
The high-bandwidth memory stacked beside an accelerator exists to keep thousands of parallel units fed, and it is expensive, hot and supply-constrained — HBM4 has been quoted around US$550 a stack. A host CPU orchestrating that accelerator has the opposite profile. It touches a lot of small, scattered objects and rarely streams enormous contiguous blocks, so it is bounded by latency and by capacity per watt rather than by raw throughput.
Spending the power budget on memory bandwidth the workload cannot use would take watts away from the accelerators, which is where the useful work happens. In a power-constrained rack, an efficient host is worth more than a fast one — a systems decision rather than a CPU decision.
The benchmark is a proxy, and Nvidia says so
The headline performance claim is roughly 1.8 times Grace on agentic workloads. Two qualifications belong with it, and Nvidia supplies both.
The measurement uses SPEC CPU 2026 as a proxy rather than a native agentic workload. A proxy is a reasonable engineering instrument and it is not the thing itself. SPEC exercises general integer and floating-point behaviour, while the claim concerns a workload with a different memory access pattern and a great deal more waiting.
Separate vendor figures put the per-clock improvement at about 1.5 times Grace and claim roughly 50 per cent more performance than x86 competitors. These are all Nvidia's own numbers from its own methodology, and none has been independently reproduced. That is normal for a Hot Chips disclosure, and it is not a verified result.
The CPU is becoming the strategic part
Vera's specifications matter less than what its existence says about where the contest is moving.
For several years the interesting silicon in an AI system has been the accelerator, with the host processor treated as necessary overhead. Designing a custom core specifically for the work of directing accelerators is an admission that the overhead became the bottleneck — that when a system is running agents rather than training runs, the machine spends a surprising share of its time on the part that decides.
It also further narrows the space for a general-purpose host CPU in these racks. Nvidia now supplies the accelerator, the CPU, the coherent interconnect between them and the fabric across the rack. The same consolidation logic is visible in Google's custom silicon arrangement with Marvell: the buyers large enough to design their own parts are doing so, and the merchant market shrinks to everyone else.
What it means from here
For operators in the region planning capacity, the practical consequence is that the host is no longer a commodity line item to be specified last. A Rubin system arrives with a Vera in it, and the CPU, memory topology and interconnect come as one decision rather than three.
That reduces integration risk and it reduces negotiating room, which is the same trade every vertically integrated platform offers. Anyone modelling total cost for an AI buildout should stop pricing the host separately, because the vendor has stopped selling it separately.
The claim worth waiting on is the performance one. Until somebody runs a real agent workload on Vera rather than a proxy, 1.8 times is a well-argued expectation rather than a measurement.
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